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The signal shown above generates two complementary control signals from input signals. These signals can be used as clock signals for the different stages of a register.
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Circuit for Generating Complementary Control Signals
The signal shown above generates two complementary control signals from
input signals. These signals can be used as clock signals for the different
stages of a register.
Binary input signals V1, V2 and V3 are provided at input
terminals IN1, IN2 and IN3, respectively, and two complementary
output signals VO1 and VO2 are generated therefrom on output
terminals OUT1 and OUT2, respectively, as follows:
VO1 = V1 + V2 + V3
VO2 = V1 + V2 + V3.
The circuit comprises four transistors T1 to T4 arranged as a current switch
circuit with transistor T5, the conduction of which is controlled through voltage
Vcs applied at its base. Input signals V1 to V3 are applied at the bases of
transistors T1 to T3, and the base of transistor T4 is connected to a reference
voltage VREF. Voltage VREF is chosen in such a way that, the circuit being
activated by making transistor T5 conductive, when one of the transistors T1, T2
and T3 is on, transistor T4 is OFF, and vice versa.
Through the arrangement of diode-mounted transistors T8 and T9 and
resistor bridge R1 to R5, with R1 + R2 = R4 and R3 = R5, the current provided at
the base of transistor T6, when at least one of the transistors T1 to T3 is OFF, is
equal to the current provided at the base of transistor T7 when transistor T4 is
Consequently, the output signals on output terminals OUT 1 and OUT 2 have
an UP level which depends on the values of the resistors and the positive