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MTL Storage Cell

IP.com Disclosure Number: IPCOM000069767D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Wiedman, SK [+details]

Abstract

The storage cell consists of two inverter stages cross-coupled in the manner of a flip-flop. Each inverter stage corresponds to a merged transistor logic (MTL/I/2/L) basic structure with injection zones P1 and P1' arranged laterally to inversely operated vertical, inverting transistor structures T2 and T2', respectively. The supply of the operating current and the coupling of the read/write signals are effected via a bit line pair B01, B11 connected to injection zones P1, P1', respectively. For addressing, only one address line X is required which is connected to the common emitters N1 of inverting transistors T2, T2'. The current injected back into the appertaining injection region, when inverting transistor T2 or T2' is conductive, is used during reading.