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This article describes a technique for reducing the memory size of a ROS LSI circuit while still providing a parity checked output.
English (United States)
This text was extracted from a PDF file.
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Parity Generation at ROS Output
This article describes a technique for reducing the memory size of a ROS
LSI circuit while still providing a parity checked output.
Many ROSs use 1/9 of the total array to produce a parity bit based on the
personality of the other 8 ROS outputs. This article describes a technique for
eliminating that personality which is used to generate the parity bit.
On a single LSI ROS chip, take the data output bits (typically 8) of the ROS
and feed them into a parity checking circuit. This circuit can take on one of
several forms including a small PLA structure, an exclusive OR tree or a ripple
parity check circuit. Since these various forms are physically much smaller than
the main ROS array, they can be designed to be placed on the chip in otherwise
wasted (or inefficiently used) silicon area. This parity output can then drive off
chip as if it had been generated by the ROS array.
The parity bit, generated in this manner, provides a parity check for all circuits
"past" the array outputs. In a typical machine environment the parity check
guards primarily against noise errors. Since the array is a controlled environment
with no unknown signal wiring near it, spurious noise is not a problem in that area
of the machine. The relatively high noise area of the machine begins at the ROS
O:CD outputs, and this circuitry is checked. This configuration will not detect a
hard failure within the ROS, and therefore must not be used on the subset of