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Parity Checking of ROS Input Word

IP.com Disclosure Number: IPCOM000069781D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Gladstein, LA Love, RD [+details]

Abstract

Existing Read-only store (ROS) LSl chips store a parity bit for each word stored in the array. However, this type of parity generation cannot catch signal revel errors which occur before or during address generation. Even when an input address has an accompanying parity bit, that bit is notted into the ROS array, since to do so would double the size of the ROS array.