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The figure shows a circuit arrangement for phasing a 1F clock relative to a 2F clock and a serial stream of bits which have been encoded in a 2-7 fixed rate run-length limited code.
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Phase Alignment of 1F and 2F Clocks
The figure shows a circuit arrangement for phasing a 1F clock relative to a
2F clock and a serial stream of bits which have been encoded in a 2-7 fixed rate
run-length limited code.
In a 2-7 fixed rate code where a 11 (binary) data word is encoded as a 1000
(binary) code word, each bit of the code word is recorded at twice the frequency
(2F) of the data word. When encoded data is read from a moving magnetic
memory as a serial bit stream, a 2F variable frequency oscillator (VFO) is used to
generate a 2F clock, which is divided down by a toggle flip-flop to generate the
1F clock. The VFO circuits also establish the phasing between the 2F clock and
undecoded 2-7 read data pulses. In order to establish proper phasing, it is
necessary to distinguish between adjacent cycles of the 2F read signal so that
the 1F clock signal is in proper phase.
In the figure, a negative 2F clock is supplied to AND-invert gate 10 whose
output is connected to 1F flip-flop 11. Each negative-going transition in the
signal from 10 causes flip-flop 11 to toggle from one state to the other.
The clock inhibit input to gate 10 generated by align control circuits 12
functions to block the first negative-going transition of the 2F signal if it is out of
phase. If it is in phase, it passes through gate 10 and toggles flip-flop 11. If it is
out of phase, the next negative-going transition of the 2F signal toggles flip-flop 11. The +1F and -1F signals fed to the ali...