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Apparatus for Discriminating Between a Bit Value Error and a Faulty Tester

IP.com Disclosure Number: IPCOM000069821D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Homan, ME [+details]

Abstract

In an apparatus for determining the Boolean value (1 or 0) within any single bit cell in a 2/N/ array selectable by an N-bit Pointer, an arrangement for discriminating between false Indication at the port of the tester jointly or severally in the presence of faults within the combinational logic used by said testers. The arrangement comprises an exclusive OR gate (on/off check) for providing an error indication only upon the joint occurrence of signals at the ports; and gating means (AND gates 25, 26) responsive to the testing of plural bit values instead of single bit values and providing indication thereof, plural bits selectively being represented through faulty logic at the port by a single signal.