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High Frequency Low Offset Peak Hold Circuit

IP.com Disclosure Number: IPCOM000069828D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Blythin, P [+details]

Abstract

The peak hold circuit shown receives an input signal at terminal 1 and stores the positive peaks of this signal on capacitor C to be provided at output 7. The input signal is applied to the base of an emitter follower transistor T(3) on line 2 whose bias is controlled by a circuit including operational amplifier 3 to maintain its emitter at DC ground. Thus, the high frequency input signals, accurately referred to ground, appear at point 4.