Browse Prior Art Database

Tool for Handling, Inserting and Soldering MOS Logic in DIP Packages

IP.com Disclosure Number: IPCOM000069846D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Ett, AH [+details]

Abstract

PMOS, CMOS, NMOS and MOS (metal oxide semiconductor) logic elements are susceptible to damage due to static electricity applying excessive voltages between input pins and grounds or supply pins. They are also subject to damage due to soldering heat. This tool provides for a means to eliminate both problems easily and at low cost. The first by shorting all pins together, and the second by heat sinking.