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Low Current Level Widest Margin Josephson NDRO Cell

IP.com Disclosure Number: IPCOM000069859D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Henkels, WH [+details]

Abstract

The NDRO (nondestructive read out) memory cell 1 of Fig. 1 basically consists of a superconducting storage loop 2 and two resistive loops 3, 4. Storage loop 2 contains a Josephson junction write gate W.G. controlled by resistive loop 4 which is driven by a Josephson junction gate G3. The binary states are "1" identical to I(circ) and "0" identical to 0. The writing of a "1" is accomplished by the coincidence of monopolar pulses on Y, Y(x) and X lines which are connected to storage loop 2 and resistive loop 4. The writing of a "0" is accomplished by erasing I(circ) (if a "1" exists) by coincidence of monopolar pulses on only Y(x) and X lines.