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Test Generation Using Data from a Deductive Fault Simulator

IP.com Disclosure Number: IPCOM000069898D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Dubler, JF Godoy, HC [+details]

Abstract

In the deductive fault simulator described in the IBM Technical Disclosure Bulletin 19, 2352-2353 (November 1976), each gate carries along with it a fault list. Each fault on the fault list would invert the output of that gate. The present article describes a scheme to use the fault list information to generate subsequent test patterns that will propagate undetected faults toward an output pin. The objective is to detect all the faults in a logic structure. Sequence Of Events: 1. A test pattern is applied to the input pins of a logic structure, and the deductive fault simulator calculates the good-machine (nonfailing) response to the pattern along with the fault list for each gate. 2.