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The circuit is designed to provide dual-phase outputs with a minimum of circuit delay while driving the highly capacitive loads of an array address decode circuit.
English (United States)
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Array True Complement Generator with Power Driver
The circuit is designed to provide dual-phase outputs with a minimum of
circuit delay while driving the highly capacitive loads of an array address decode
Transistors T1 through T6 form a high speed, medium power current switch
with a high impedance emitter follower input and with level shift diodes T2 and T5
to eliminate the need for both a clamp diode at the input node and saturation
clamps on the current switch transistors T3 and T4.
Diode-connected transistors T2 and T5 prevent saturation of the current
switch by shifting the signal at the base nodes of T3, T4 to levels which
guarantee that the base-collector junctions of T3, T4 will never be forward
Down-level clamps T7 and T8 establish the down levels at the collectors of
T3 and T4, thus making absolute resistor values and tracking noncritical.
The pseudo push-pull driver output circuits consisting of T9-T10 and T11-T12
provide high current up-level and down-level drive capability while adding only
Emitter follower transistors T9 and T11 produce up-level drive and buffer the
high-speed switching portion of the circuit.
Current sink transistors T10 and T12 remain constantly on and,
consequently, do not require inverted drive and do not produce switching delay.
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