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Semiconductor Die with Wiring Skirt (Packaging Structure)

IP.com Disclosure Number: IPCOM000069920D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Ecker, M Olson, L [+details]

Abstract

The disclosed structural technique may be generally summarized by the following features: 1. A semiconductor chip or chips mounted on membrane-like insulating members and said membrane-like members to provide for multilevel wiring and interconnection between the chip or chips and a secondary wiring structure. 2. A foam rubber pad or pads for biasing the semiconductor chip or chips against the module protective enclosure as well as accommodating induced chip motion or variations. 3. Considerable reduction in module internal thermal resistance.