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A multi-step first layer metal wiring to a transistor with poly-silicon contacts the base and the metal directly contacts the emitter. It also uses the dielectric isolation to reduce isolation capacitance.
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Transistor and Wiring with Multi Step First Layer Metal
A multi-step first layer metal wiring to a transistor with poly-silicon contacts
the base and the metal directly contacts the emitter. It also uses the dielectric
isolation to reduce isolation capacitance.
The process involves the formation of dielectric isolated monocrystalline
silicon pockets by standard techniques. Fig. 1A shows isolation regions 1,
collector-base isolation region 2, subcollector 3, N+ reach-through 4 and P+ base 5. A layer of silicon dioxide 7 and a layer of silicon nitride 8 are formed over the
surface of the structure. The base contact holes are opened through layers 7
and 8 by conventional etching techniques. Polycrystalline silicon doped with
boron layer 9 is formed over the surface, as shown in Fig. 1A.
Reactive ion etching (RIE) or a combination of reactive ion etching with
chemical etching for the silicon nitride through the poly-silicon for emitter,
collector contact definition and first metal top/bottom (pedestal/valley) geometries
is done. The N+ shape will be determined partially by this poly-silicon shape
caused by the geometry obtained as shown in Fig. 1B. The etched poly-silicon
layer 9 is coated with chemical vapor deposited silicon nitride (Si(3)N(4)) layer 10.
The Si(3)N(4) layer 10 is etched by RIE, leaving Si(3)N(4) only around the
neck. The SiO(2) layer 7 is etched. The N+ emitter region 11 is implanted while
using block-out mask. Part of the poly-silicon is exposed t...