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Metal Silicide Layer for the Post Emitter Base Implantation Process

IP.com Disclosure Number: IPCOM000069925D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Chu, WK Horng, CT Schwenker, RO [+details]

Abstract

In post emitter base implantation, the base impurity is implanted through regions with a dielectric layer (e.g., 1600 angstrom Si(3)N(4), 1800 Angstrom SiO(2)) and without a dielectric layer. The partial structure of such a transistor, as shown in Fig. 1, comprises a base region 1, emitter region 2, and a dielectric layer 3 with openings 4, one being above the emitter 2. As indicated by A, a narrow base width results and causes emitter-base pinching problems.