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Randomization of Deterministically Generated Test Patterns

IP.com Disclosure Number: IPCOM000069932D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Goel, P Horstmann, PW Rosales, BC Snethen, TJ [+details]

Abstract

Random test patterns used in conjunction with deterministically generated test patterns are effective for level sensitive scan design (LSSD) [*] logic networks. Classically, a random test pattern is generated by randomly assigning a logic 0 or logic 1 to each external input of a logic network. After the first few random patterns have been fault simulated, the average number of faults detected by each subsequent random pattern can drop off sharply. Consequently, one rapidly approaches the break-even point at which the random pattern generation should be replaced by deterministic test generation.