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This technique provides a way of concealing parallel failures in the parallel section of a series-parallel-series (SPS) array organization by providing a dynamic substitution of a good segment.
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Dynamic Series Parallel Series Array Configuration
This technique provides a way of concealing parallel failures in the parallel
section of a series-parallel-series (SPS) array organization by providing a
dynamic substitution of a good segment.
In a charge-coupled device (CCD) memory application, the SPS
organizational structure is used to minimize on-chip peripheral circuitry and
power consumption. A plurality of these SPS structures make up a memory
array chip. This SPS structure consists of two series registers as the input and
output network of the parallel section. The parallel section is made up of many
segments which propagate the bulk of the stored information. A failure in any
one of these parallel segments could impair the integrity of the whole SPS
The figure shows the additional parallel segment 10 and location register 12
to a normal SPS array structure 18. This provides a means for removing the
effects of a parallel segment failure by substituting another parallel segment.
This is accomplished by the location register 12 which has data only stored in the
location corresponding to the failure segment. This "location register" is identical
in length to the input/output series registers 14 and 16 of the SPS array and is
clocked at the same rate. It should be noted that the location register 12 and
substitution segment 10 do not have to be physically located within the same
As a result, a dynamic means is available which can relocate un...