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This article describes a highly integrated delay circuit for generating defined pulse widths, with a transistor and an RC element which are both merged in a single isolation pocket to save space.
English (United States)
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Integrated Delay Circuit
This article describes a highly integrated delay circuit for generating defined
pulse widths, with a transistor and an RC element which are both merged in a
single isolation pocket to save space.
The equivalent circuit diagram of Fig. 1 shows a transistor T with a resistor R
in the collector circuit connected to operating voltage +V. Capacitance C is
connected parallel to the collector-emitter path of transistor T. Input I is
connected to the base and output 0 to the collector of transistor T. Resistor R
and capacitance C form the delay element.
Referring to Fig. 2, an N- expitaxial layer 2 is applied to P-substrate 1. The
isolation pocket accommodating the delay circuit structure is delimited by P+
subisolation zone 3 and the adjoining P top isolation zone 4 extending up to the
surface of N- epitaxial layer 2. A buried N+ zone, occupying a partial area of the
isolation pocket, forms subcollector 5 of transistor T, which is completed by the
superimposed zone of N- epitaxial layer 2 as collector zone 6, a P base zone 7,
an N+ emitter zone 8, and an N+ collector reach-through zone 9 extending down
to subcollector 5.
In the partial area of N- epitaxial layer 2 not occupied by subcollector 5, an
extensive P zone 10 is simultaneously embedded with P top isolation zone 4 and
base zone 7. P zone 10 is preferably connected to P top isolation zone 4, so that
no separate contact to ground is needed. P zone 10 and N+ zone 11, the latter