Browse Prior Art Database

Ion Implanted High Voltage MOSFET Device

IP.com Disclosure Number: IPCOM000069975D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Oleszek, GM Perner, FA Spencer, OS Wang, PP [+details]

Abstract

An Al-gate, SiO(2) dielectric, n channel MOSFET is shown that is designed to achieve drain breakdown voltages greater than 50 V without sacrificing the current handling capability of the MOS transistor. Voltage capability is achieved using high resistivity silicon, and current capability is achieved from a "DMOS type" horizontal structure. The design of this device is directed to be compatible with conventional low voltage MOS fabrication technology in which only a single dielectric is used (SiO(2)), impurity deposition is by ion implantation (I/I), and the metallurgy is Al-Cu. Both low voltage and high voltage device structures may be formed on the same IC chip by selective masking of ion implantation.