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Self Aligned Gate FET Process with Source Drain Diffusion Prior to Gate Definition Disclosure Number: IPCOM000070003D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21

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Esch, RP [+details]


This article describes a self-aligned FET structure using a process sequence substantially different from those observed in current literature. Existing schemes use the growth of the gate oxide early in the process with the source-drain deposition and drive-in occurring late in the process. The process described provides the source-drain step early in the process with gate coming later. Existing processes use silicon nitride or the polysilicon patterns to define the source-drain spacing, whereas this process uses a thermal silicon dioxide pattern. Existing processes have to provide field tailoring implants at the beginning of the process which get redistributed during subsequent hot processing steps, whereas this process provides the implant after the high temperature processing is completed.