Physical to Logical Checking of FET LSI Chips
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Feb-21
This article describes a method for the physical-to-logical checking of FET LSI chips. The circuit recognition algorithms described in the two preceding articles are used as a basis for FET circuit modelling. The resulting models are used to recognize the physical circuitry associated with each logic block in the logic design. Techniques for handling the swopability of logic inputs during the circuit recognition process and the ensuing logic comparison are discussed.