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Circuit for a High Performance Register Stack

IP.com Disclosure Number: IPCOM000070167D
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Eardley, DB [+details]

Abstract

The figure shows the circuit diagram for a register stack of M words. Each word is N bits long. There are M x N bit storage circuits. Each bit storage circuit consists of the NPN transistors T1, T2, T3, T4, T5, T6 and T7, three resistors R1, R2 and R3, and two Schottky barrier diodes D1 and D2. The peripheral circuit required to write data into a bit position consists of transistors T8, T9, T11 and T12 and resistors R6 and R7. The peripheral circuit required to read data from each bit position consists of transistor T10 and resistors R4, R5 and R8.