Decode Hold Down
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21
A decode hold-down circuit is provided to prevent the output signal from unselected decodes from being capacitively coupled to a higher voltage level, thereby inducing false signals into a memory device. This device is necessary in single-device memories where a bit line connects a series of cells to the sense circuit which is utilized to detect the storage of logical signals. During a memory cycle, the bit line decreases and increases in voltage levels. During these voltage shifts, the bit line capacitively couples to the decode outputs. Since the decode output traverses many bit lines, false signals can be generated.