TTL To MOS Driver
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21
The circuit depicted in the drawing is a high-speed memory capacitance driver that pulls and remains within a V(ce)(sat) of V(cc2) using only two power supplies. The circuit combines the techniques of Schottky clamping, PNP pullup, bootstrapping and current limiting in one driver.