Browse Prior Art Database

Polysilicon Gate FET Process with Substrate Contacts

IP.com Disclosure Number: IPCOM000070197D
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Soderman, DA [+details]

Abstract

Semirecessed oxide structures for n-channel MOSFET devices have many features which allow high density and power performance tradeoffs. This is becoming an industry standard. However, the usual implementation of this technology results in substrate contact being made on the backside of the chip via the ceramic-plastic encapsulated package. It has also been shown that the addition of a substrate voltage generator circuit on the chip improves circuit performance and eliminates one system power supply and one pin in an already pin-limited package. Newer beam lead packaging techniques have no easy method of making electrical contact to the backside of the semiconductor chip.