Lateral PNP Clamped Resistor Load Device
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21
In order to enhance the speed of logic circuits, it is often desirable to limit the voltage swing of the output node of a logic gate by clamping the down-level voltage at same maximum swing relative to the up level. In some linear applications, it is also desirable to clamp the voltage levels to some safe operating range.