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High Performance Parallel Planar Package Disclosure Number: IPCOM000070203D
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21

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Related People

Carter, RS Emmons, WD Silveri, RA [+details]


The packaging arrangement permits the use of high performance LSI (large-scale integration) single chip modules. This design significantly increases the packaging circuit density at the frame level and eliminates a level of packaging. The arrangement incorporates features that permit significant improvement in density, cost and performance.