Fast Zero Sum Detection Circuit for BCD Adder/ Subtractor
Original Publication Date: 1978-Aug-01
Included in the Prior Art Database: 2005-Feb-21
U. S. Patent 3,983,382 describes a circuit which will detect a zero sum from a binary adder without waiting for the sum outputs to be resolved at the adder output. This article describes a similar function for a BCD (binary coded decimal) adder.