Shift Register Latch for Synchronizing Channel and Processor Data Transfer
Original Publication Date: 1978-Sep-01
Included in the Prior Art Database: 2005-Feb-21
The above circuit synchronizes signals between a processor and a channel. The channel operates with a clock having a fixed sequence of times designated C0, C1, C2 and C3. The processor operates with a clock having a variable length sequence of times designated T0, T1.... The processor and channel clocks rise and fall together, but the channel clock sequence can start at various points in the processor clock sequence.