Browse Prior Art Database

Clocking for Shift Register Latches

IP.com Disclosure Number: IPCOM000070331D
Original Publication Date: 1978-Sep-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Hester, RL Kobesky, LJ [+details]

Abstract

A shift register latch (SRL) is a master-slave latch in which an input stage (L1) receives data under an A phase clock and an output stage (L2) receives data from the L1 stage under a B phase clock. The data to the input of the L1 stage is supplied from an external combinatorial network for the normal operating functions of a data processing system, or it is supplied from another latch when the latches are interconnected for a scanning operation for diagnostics. See U. S. Patent 3,806,891.