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Lookahead Technique for Speeding Up Fault Simulation for LSSD Logic Networks Disclosure Number: IPCOM000070345D
Original Publication Date: 1978-Sep-01
Included in the Prior Art Database: 2005-Feb-21

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Goel, P [+details]


Present-day fault simulation for level sensitive scan design (LSSD) logic circuits is quite costly [*]. The disclosed technique will allow substantial speed-up of the fault simulation process, providing a cost reduction.