Browse Prior Art Database

Lookahead Technique for Speeding Up Fault Simulation for LSSD Logic Networks

IP.com Disclosure Number: IPCOM000070345D
Original Publication Date: 1978-Sep-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Goel, P [+details]

Abstract

Present-day fault simulation for level sensitive scan design (LSSD) logic circuits is quite costly [*]. The disclosed technique will allow substantial speed-up of the fault simulation process, providing a cost reduction.