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Custom Programmable Logic Arrays on STL Masterslices

IP.com Disclosure Number: IPCOM000070349D
Original Publication Date: 1978-Sep-01
Included in the Prior Art Database: 2005-Feb-21

Publishing Venue

IBM

Related People

Authors:
Dansky, A Kapushoc, P Swietek, D Ting, YM Varadarajan, H [+details]

Abstract

This disclosure describes two techniques for varying the size of programmable logic array (PLA) macros. The first method uses a modular approach to columns of cells, as needed. The height of the AND array can be changed by adding more input decoders. This customizing of the array size is performed by interconnecting the required number of circuits and output diodes, as required. Only the personality levels will be affected from one Part Number to another.