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Precharge system for interconnection bus in a multi processing architecture Disclosure Number: IPCOM000074324D
Original Publication Date: 2005-Feb-23
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 48K

Publishing Venue



A system for improving interconnections in a multi processing system involving large amounts of modules is disclosed. The disclosed system allows reducing the DC power dissipation and increasing the bus maximum frequency. Only few additional devices are needed. This system can be applied when several ZISC (Zero Instruction Set Computer) modules are connected together.

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Precharge system for interconnection bus in a multi processing architecture

Disclosed is a precharge system allowing the interconnection of a large number of electronic modules using a common bus. In a multi processing system involving hundred or thousand Processor Elements (PEs) an important point is the interconnection between all PEs. There are two types of interconnections: interconnections inside a chip, and interconnections outside a chip. Because geometric dimensions are larger outside a chip, wires on board are more capacitive and connection gains are more important.

A common way to connect together many modules is to use a common bus with open collectors' circuits. For example the ZISC (Zero Instruction Set Computer) circuit (a parallel nearest neighbor classifier) uses such common bus.

    A major drawback of this type of circuit is the speed of this common bus. This common bus use open collector circuits to perform the AND operation between all module outputs and when the number of modules is high, the capacitive load of this bus can be very large and thus if reduces the maximum speed of this bus. Due to this architecture, an external tie up resistor is needed. This resistor needs to have a low value to allow a fast signal rising time. But these low values imply high power consumption when a module applies a low level state at the output.

    An alternative is to use some additional logic, but this alternative needs additional circuits and adds incompressible delay to perform the AND operation between all the modules.

    Therefore there is a need for a new system that increases the speed and that avoids high power consumption.

    The main idea is to use a precharge system for the intercommunication bus. The precharg...