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# Pseudo Random Count Generator

IP.com Disclosure Number: IPCOM000074678D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 29K

IBM

## Related People

Benjamin, JR: AUTHOR [+3]

## Abstract

Simulated random bit patterns within a shift register are provided by logically interpreting the shift register contents and using the interpretation results to control gating of count pulses into the shift register.

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Pseudo Random Count Generator

Simulated random bit patterns within a shift register are provided by logically interpreting the shift register contents and using the interpretation results to control gating of count pulses into the shift register.

Shift register 20 is assumed for exemplary purposes to have 16-bit positions 0 - 15. Sequential pulses introduced at 21 cause 20 to shift and store a 1 in position 0 as long as AND 22 output is up. When the output of 22 is down, pulses at 21 cause 20 to shift but effectively results in storing a "0" in position 0. Assuming 20 initially clear, the first five pulses at 21 will cause 1's to be stored in bit positions 0 - 4. At that time, Exclusive OR 23 will generate an output which will also cause Exclusive OR 24 to produce an output and thus drop the output of 22 via invert 25. The next pulse at 21 causes 20 to shift so that 1's are present in positions 1 - 5 but a "0" is in position 0. After the next two shifts of 20, bits 4 and 7 will be present so that 23 - 25 will cause 22 to again produce an output and resume introducing 1's into 20. A similar result is produced from Exclusive OR 26 when either bit 12 or 14 is present, while bits 4 and 7 are either both present or both absent. AND 28 senses when all bits are present in 20 so as to drop the output of 22 via invert 29 if such a byte should result. Thus, 28 functions to insure that 20 will be full for no more than one pulse at 21. By this particular arrangement of using...