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# Parity Prediction for an Arithmetic and Logical Unit

IP.com Disclosure Number: IPCOM000074699D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 55K

IBM

## Related People

Miessler, MH: AUTHOR

## Abstract

The diagram shows a logical circuit for parity prediction in an Arithmetic and Logical Unit (ALU). The circuit is designed for an ALU having two 4-bit input operands P0, P1, P2, P3; Q0, Q1, Q2, Q3 and a Carry In Cin; and which generates logical functions of the input operands To, T1, T2, T3 and C0, C1, C2, C3, wher T0 = P0 v Q0 etc. and G0 = P0.Q0 etc.

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Parity Prediction for an Arithmetic and Logical Unit

The diagram shows a logical circuit for parity prediction in an Arithmetic and Logical Unit (ALU). The circuit is designed for an ALU having two 4-bit input operands P0, P1, P2, P3; Q0, Q1, Q2, Q3 and a Carry In Cin; and which generates logical functions of the input operands To, T1, T2, T3 and C0, C1, C2, C3, wher T0 = P0 v Q0 etc. and G0 = P0.Q0 etc.

The circuit uses the logical parities for the prediction of the arithmetic parity as follows: The parity for four types of ALU functions is given by Binary Sum or Difference PS = PT v PC v F for Subtraction the Subtrahend bits are inverted and Cin forced to 1.

(Image Omitted)

The expressions shown above and the circuit can be expanded for operands consisting of 8-bits with the logical parity still being used to predict the arithmetic parity. for example:

Equation 2 below represents a fast realization of F corresponding to the 4-bit version given above by equation 1:

1

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