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# Single Precision Arithmetic Algorithms

IP.com Disclosure Number: IPCOM000078739D
Original Publication Date: 1973-Feb-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 65K

IBM

## Related People

Alexander, DC: AUTHOR [+1]

## Abstract

Multiplication and division routines for small computers are usually designed to calculate only double-precision products and to accept only double-precision dividends, thus simulating multiply/divide hardware. Often, however, a user prefers single-precision representations. Algorithms are presented for single-precision binary multiplication and division, designed to optimize execution time and storage requirements. The multiplication algorithm is shown in flow chart form in Fig. 1. Since the algorithm used does not tolerate negative multipliers, the multiplicand is given the sign of the product and the multiplier is made positive.

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Single Precision Arithmetic Algorithms

Multiplication and division routines for small computers are usually designed to calculate only double-precision products and to accept only double-precision dividends, thus simulating multiply/divide hardware. Often, however, a user prefers single-precision representations. Algorithms are presented for single- precision binary multiplication and division, designed to optimize execution time and storage requirements. The multiplication algorithm is shown in flow chart form in Fig. 1. Since the algorithm used does not tolerate negative multipliers, the multiplicand is given the sign of the product and the multiplier is made positive.

In the single-precision multiplication, arithmetic overflows can occur; to enable detection of these overflows, separate registers are used to contain the multiplier and the cumulating product.

To avoid using still another register for a loop counter, one bit of the multiplier is used as an end-of-word mark. This is possible because the multiplier is nonnegative and thus has a spare bit, and because the carry bit acts as a one-bit extension to the multiplier register. Using the multiplier as a shift counter not only conserves registers, but also execution time since no additional instructions are required to increment the counter.

During the multiplication, it is necessary to shift the product left; the operation is performed by adding the product to itself thus insuring that arithmetic overflows...