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# Algorithm for Generating a Complete Minimum Set of Test Patterns for Combinational Circuits

IP.com Disclosure Number: IPCOM000078780D
Original Publication Date: 1973-Mar-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 4 page(s) / 93K

IBM

## Related People

Chia, DK: AUTHOR [+4]

## Abstract

A test pattern generation method using the Boolean difference concept and the algorithm for implementing it is developed. This method gives a minimum set of test patterns that can be used to detect all detectable faults in an irredundant combinational network. (Image Omitted)

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Algorithm for Generating a Complete Minimum Set of Test Patterns for Combinational Circuits

A test pattern generation method using the Boolean difference concept and the algorithm for implementing it is developed. This method gives a minimum set of test patterns that can be used to detect all detectable faults in an irredundant combinational network.

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The problem of test pattern generation for testing logic networks can be simplified, by considering various "signal propagation paths separately. A pair of test patterns is selected for each such path.

The Boolean difference of the output with respect to a primary input through a specific path, gives the complete set of test patterns for testing this path. The identifying of the various paths and the obtaining of the Boolean difference for each path is simplified, by recognizing the following relations:

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Any other gate functions of X and Y can also be characterized for the Boolean difference. These simple relations are used to obtain the Boolean difference chain over a specific path. For any path P(i), i.e.,

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Equation (7) is computed by using Equations (3), (4), (5) and (6), which is considered as a Boolean difference chain and is denoted by P(i). Test Pattern Generation Algorithm.

A program has been written in FORTRAN for implementing the test pattern generation using Boolean difference. The flow chart is shown in F. 1.

The generation test pattern algorithm is as follows...