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Junction Isolation Structure for Semiconductor Devices

IP.com Disclosure Number: IPCOM000080145D
Original Publication Date: 1973-Nov-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 47K

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In producing this structure all diffusions required to make a device are made from the surface.

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Junction Isolation Structure for Semiconductor Devices

In producing this structure all diffusions required to make a device are made from the surface.

A N+ phosphorous diffusion is made through window 10 in SiO(2) layer 12, resulting in a diffused region 14 in semiconductor wafer 16 shown in A. The diffusion can be made in a capsule in the conventional manner, which results in a profile 18 shown in B. The wafer 16 is then heated in a vacuum to a high temperature causing out-diffusion of the impurity adjacent the surface, resulting in a impurity distribution having a profile depicted by 19 in C.

A high-vapor pressure of the phosphorous impurity at the surface will out- diffuse, dropping the impurity concentration at the surface significantly below that deeper into the device. Since the concentration of the phosphorous near the surface is low, shallow diffusion devices such as bipolar transistors, field-effect transistors or Schottky barrier diodes can be formed near the surface. The profile of a bipolar device, which can be formed by conventional techniques, is depicted as profiles 20 and 21 in D.

In a device utilizing the isolation technique, a N type region surrounded by a P- region is created without the necessity of a N epitaxial deposition. The profile of the impurity in the end-diffusion region 14 is such that the surface has a high resistivity to give good breakdown voltage, while having a subsurface region with a high conductivity to reduce collector resis...