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AC Test Pattern Generation for Sequential Logic

IP.com Disclosure Number: IPCOM000080524D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 3 page(s) / 32K

IBM

Chao, CC: AUTHOR

Abstract

In accordance with the present technique, AC test patterns are applied to a sequential logic circuit through sensitive paths created by DC sequential patterns from the primary inputs of a chip to its outputs.

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AC Test Pattern Generation for Sequential Logic

In accordance with the present technique, AC test patterns are applied to a sequential logic circuit through sensitive paths created by DC sequential patterns from the primary inputs of a chip to its outputs.

The present technique is aimed at improving AC test pattern generation quality as well as quantity. It will supplement AC patterns to test those logic blocks which could not previously be reached. The present technique utilizes DC sequential test patterns as a source for AC pattern generation, since normally a logic chip has to go through DC functional testing, and these patterns are readily available. DC test patterns used as a source may not necessarily be in sequential order, as for example a random DC pattern generator. Even if the DC test patterns are in sequential order, there is always a possibility that no indication is given where a sequence begins and ends.

DC test pattern generation is currently based on stuck-fault theory. Any stuck fault (logic 1 or 0) at a logic port presents a binary change between a good and bad chip, which is reflected at a chip's primary output as a binary difference. This phenomenon is utilized in an AC sense. If the DC test pattern is applied to good chips, and a logic step transition is applied, as from a logic 0 to a logic 1, at a primary input, and if there is a corresponding logic step transition showing up at a primary output, the logic transition at the primary input can be reversed, as from a logic 1 to a logic 0, and if the same output shows also a reversed step transition, then a single pulse AC test pattern is obtained. It should be realized that an AC pulse is merely made by two logic step transitions, for example, positive pulses made out of a logic 0 to 1 transition, and a logic 1 to 0 transition.

In highly sequential circuits it usually requires a series of DC sequential patterns, applied consecutively to the chip under test, to precondition certain logic blocks to pave a sensitive path(s), and the sensitive path(s) may also be AC sensitive. It is possible for the paths created for all primary input faults to be sensitive. A set of DC sequential patterns, say M patterns, may contain multiples of faults, for instance, at pattern number N (N being smaller than M) it creates a sensitive path for a particular stuck fault, and at pattern P (P is smaller than M, but larger than N) there is created a other sensitive path and so on. Those paths may be AC sensitive also. Moreover, there are possibilities that extra AC sensitive paths may be created by chance, due to DC pattern sequences unrelated to stuck faults.

DC sequential test patterns may be grouped into independent subsets, each subset consisting of a complete set of sequential patterns for detecting single or multiple stuck faults of a...