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Asynchronous Latch Circuit Disclosure Number: IPCOM000080535D
Original Publication Date: 1974-Jan-01
Included in the Prior Art Database: 2005-Feb-27
Document File: 2 page(s) / 26K

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Jordan, PV: AUTHOR


This circuit will detect the occurrence of a metastable output from a latch 10.

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Asynchronous Latch Circuit

This circuit will detect the occurrence of a metastable output from a latch 10.

A metastable condition occurs when either the data or clocking pulse is rising while the other is falling. The latch 10 being unable to decipher the situation enters the metastable state, and produces an output signal that falls between the usual latched and unlatched outputs. To overcome the problem, two circuits 12 and 14 with different threshold levels are used to detect the differences between a metastable state output condition and a normal output condition. The threshold levels of devices 12 and 14 are such that neither responds to the down output condition and both respond to an up output condition of the latch 12.

When a metastable condition occurs, the circuit 14 with the low-threshold level will react. However, the circuit 12 with the high-threshold level will not respond, producing a signal causing the exclusive OR circuit 16 to produce a down level. So long as the exclusive OR circuit 16 is at an up level the latch will provide an output signal. On the occurrence of a down level, the latch 18 will not latch.


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