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Error Correction Apparatus Disclosure Number: IPCOM000081931D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 60K

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Marshall, JW: AUTHOR


Efficient buffering pointer control reduces hardware and time requirements, for error correction processing serially received high-speed data bits.

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Error Correction Apparatus

Efficient buffering pointer control reduces hardware and time requirements, for error correction processing serially received high-speed data bits.

The serial data has the code words interleaved for enhancing error detection and correction. The data is transmitted in frames 1-N separated by a resynchronization or framing character, identified as frame character. Each frame has a corresponding byte of each and every code word. Frame 1 has bytes A1-F1, i.e., the first byte of code words A-F. In a similar manner, frame 2 has the second byte of each code word A2-F2, etc., for as many frames as the message contains. Each frame is designed to contain error pointing signals to be used for error correction purposes, such as taught by Hinz, Jr., in U.S. Patent No. 3,639,900 and as hereinbelow set forth.

Intermediate or partial error syndromes based on received data bits are calculated and stored on a frame-by-frame basis. Such serial interleaved calculation yields an error correction format shown in a rectangle, wherein the code words A-F are represented by the columns, and the frames are represented by the rows. Pointer bounds extend along the horizontal rows.

If there are two pointers in the array, for example, in bytes 1 and 4, each of the code words A-F receive those two pointers for pointing to the two bytes in error in each and every code word. In this manner, the two track and error correction taught by Hinz, Jr., is applied to serial data transmission. For error detection and correction purposes, the frame character separating the various frames can be ignored or can be used as a part of the error correction system which is beyond the scope of the present description.

In the simplified block diagram, the data source supplies data through a data- in switch to the illustrated error detection and correction circuits. Simultaneously therewith, error pointer signals are supplied to the pointer decode for gating into the two pointer stores synchronously with syndrome generation by shift registers SR1 and SR2. Timing of such circuits is omitted for clarity.

As a first data byte comes in, SR1 and SR2 are operated synchronously; the generated partial syndromes are stored in the syndrome 1 and syndrome 2 stores; each store has an F-byte capacity. On succeeding bytes 2-F, the stored partial syndromes are read out of the two syndrome stores and fed back into the SR1 and SR2 to be matrix multiplied with the data-in, in accordance with U.S. Patent No. 3,508,194. Additionally, the final syndromes are supplied to an o...