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Radar Digital Scan Converter Disclosure Number: IPCOM000082318D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 71K

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Described is a digital scan converter which provides a slow-scan conversion for rho-theta to a high refresh interlaced rho-theta scan.

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Radar Digital Scan Converter

Described is a digital scan converter which provides a slow-scan conversion for rho-theta to a high refresh interlaced rho-theta scan.

Fig. 1 is a block diagram of the digital scan converter. The video input 1 is quantized into two or more bits in which a hard-limit precedes the analog-to- digital conversion. The radar processor control 2 supplies the sampling timing for clocking the analog-to-digital conversion, and the timing is dependent on the video bandwidth. The operator may vary the signal-to-noise ratio for the threshold on line 3 prior to the analog-to-digital conversion. The quantized output is stored in a presummer register 4. The presummer recirculates the N listening period of the radar input. The register length is S samples of two bits each.

The presummer 4 adds the S samples for each of the N listening periods in which the number of presums in the window is programmable, and depends on the blip-scan ratio. The presum of N listening periods is then averaged and rescaled in the rescaler 5 to two bits per sample. The presummed range of S samples is then shifted to the persistence control function 6.

The persistence control 6 reads from memory 7 the previous radar antenna scan listening period of S(n-1) samples which was stored. These samples of the previous radar scan have from one to three tone levels subtracted, as determined by the operator input 8 on persistence control 6. The result of this subtraction is then added to the newest presummed S samples. An average of this addition is performed and the result for all samples are stored (written) in memory 7 with the new azimuth position. The functions of controlled persistence and image freeze is included in this system.

The memory 7 is organized in odd and even fields for refresh, so that every other presummed output is located in an odd field block or even field block of memory. The data input being processed is a slow update, whereas the refresh output is a fast access presenting a minimum sensitivity problem.

The radar processor and control 9 provides a capability for range-gating the input, such that improved range resolution over particular space volumes is possible.

The refresh control 10 decodes the azimuth data stored with each listening period. It generates from a read-only memory, sine/cosine output through a binary-weighted reference. The + delta X and + delta Y sweep voltages are generated at 11 for the odd and even field refresh of the cathode-ray tube (CRT). The field rates are equivalent to 60HZ with frame times of 30HZ (or equivalent) above eye flicker threshold. These +/- delta X and +/- delta Y are summed at the CRT display deflection with Xo and Yo position.

The refresh control 10 has priority to memory access for a read. The memory read access is 800 nanoseconds...