Browse Prior Art Database

# Ring Counter

IP.com Disclosure Number: IPCOM000082808D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 38K

IBM

## Related People

Cukier, M: AUTHOR

## Abstract

This ring counter is a shift register at the input of which a logical combination of the shift register contents is fed back. With a given number of bits, a ring counter is fully defined when the feedback logic is defined.

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Ring Counter

This ring counter is a shift register at the input of which a logical combination of the shift register contents is fed back. With a given number of bits, a ring counter is fully defined when the feedback logic is defined.

Consider, for instance, that a ring counter is made of a N-stage shift register SR. The output of each stage is fed to a decode logic with 2/N/ outputs. 2/2/N/ OR'ed combinations of the decode outputs may be provided as an input fed back to the shift register SR. Each one of these 2/2/N/ combinations gives a different logic rule defining one function of the ring counter, with a given number of steps or states the shift register may be on.

This logic rule is defined by a word X of 2/N/ bits. Among these 2/N/ bits, some bits are redundant (outputs corresponding with input combinations that never occur). This can be taken into account to simplify the feedback logic of the counter. On the other hand, as the choice of the rule defines the type of counter obtainable, a multipurpose ring counter may be built by using a simple logic for closing switches to perform the desired rule and function.

These properties might be shown on a ring counter which could store up to 2/8/ different counts. The shift register SR has three stages as shown in the figure. Assuming that the register contents are a(2), a(1), a(O) each "a" may either be equal to 0 or to 1. For each value of the SR contents, one out of the eight decode outputs will be at a high-logic level.

Now, each one of the eight decode outputs may be either fed or not to the input of an OR circuit through a combining switching network. Combining, therefore, provides 2/2/3/ = 256 possible functions X of the eight switches S(1) through S(8), and for each combination of S(1) to S(8), the ring counter will count up go a different number of steps If S = 1 when the switch is closed and 0 when it is opened, X may have any one out of the 256 values; S(8) S(7) S(6) S(5)

S(4) S(3) S(2) S(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1.

It can be seen that whenever S(1) = 0, the counter is locked on 000. Furthermore, certain X bits are indifferent and this remark might be used to minimize hardware.

Shown below, for instance, is how, by applying those considerations, the hardware may be minimized for obtaining a 5, 6, 7 or 8 step counter:
First: 5 steps X=11101110 S(1)=S(2)=S(3)=S(5)=S(6)=S(7)= 1 S(4)=S(8)=0

Sequence Input

a(2) a(1) a(0) I

0 0 0 1

1 0 0 1

1

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1 1 0 1

1 1 1 0

0 1 1 0

0 0 1 1

1 0 0 1

I = a(2)...