Browse Prior Art Database

# Functional Simulation of Data Passing through Large Shift Registers

IP.com Disclosure Number: IPCOM000084202D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 53K

IBM

## Related People

Leonard, MA: AUTHOR

## Abstract

In logic simulation involving operations on data in large shift registers, the task of setting up stimulus cases tends to be complex and dominates many other aspects of the system. The key function is to lay out the model shift register with one byte for each bit and, to permit the expansion of the input data to be effectively averaged over the shift cycles, precede the area with a holding area containing expanded data which has not yet entered the simulated register. (To avoid confusion, the simulated shift register will be referred to as the matrix.)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Functional Simulation of Data Passing through Large Shift Registers

In logic simulation involving operations on data in large shift registers, the task of setting up stimulus cases tends to be complex and dominates many other aspects of the system. The key function is to lay out the model shift register with one byte for each bit and, to permit the expansion of the input data to be effectively averaged over the shift cycles, precede the area with a holding area containing expanded data which has not yet entered the simulated register. (To avoid confusion, the simulated shift register will be referred to as the matrix.)

A general register is designated to address and, thereby, define the first bit of the matrix. Shifting of the matrix is accomplished by simply decrementing this register. For variable length or large data input, a control must be kept to determine when the data expanded has been used up and more data must be prepared. For smaller quantities of data, an entire sequence can be prepared initially.

The mechanism can be illustrated by considering a matrix which is initially zero, a data record of less than double the size of the matrix, and a holding area the same size as the matrix.

Fig. 1 shows how the data is initially loaded. If required, the logic to be simulated may be exposed to the matrix in its initial state. Decrementing the register pointer by 1 has the effect of shifting the first bit into the matrix.

Fig. 2 illustrates the state after several shifts. the area of storage designated as the matrix has actually shifted to the left. The effect is that data has shifted into the matrix and some of the initial "0's" have dropped off the right end.

Fig. 3 illustrates the point at which more data must be provided. Note that the initial 0's have all dropped off. The initially loaded data is now moved to replace the initial 0's, the pointer register is returned to its initial location, the remaining data...