Surety is performing system maintenance this weekend. Electronic date stamps on new Prior Art Database disclosures may be delayed.
Browse Prior Art Database

Complementary Current Switch

IP.com Disclosure Number: IPCOM000084239D
Original Publication Date: 1975-Oct-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 38K

Publishing Venue


Related People

Blumberg, RJ: AUTHOR [+2]


The circuit depicted in the drawing is a complementary current switch, which employs both NPN and PNP transistors.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Complementary Current Switch

The circuit depicted in the drawing is a complementary current switch, which employs both NPN and PNP transistors.

The two PNP transistors TP0 and TP1 are conducting all of the time. The external voltage, VT (-1.5 volts) supplies the base voltage and resistors R0 and RI set the current IPNP demanded by the PNP transistors. The voltage at V0 and VI is one VBE above VT or approximately -0.7 volt. The current source ICS must be set greater than the ICPNP current. The ICS current source may either be a resistor or a constant-current source transistor.

Assume that voltage inputs V1, V2 and V3 are in a downlevel below the internally generated VREF = -1.25 volts. This means input transistors T1, T2 and T3 are off and TR is on and conducting ICS current. Because ICS is greater than ICPNP, transistor TEI starts to conduct and the inphase output VCI is then one VBE drop below VI or at approximately a -1.5 volts downlevel. The PNP transistor TP0 is still conducting and the collector current ICPNP flows through the Schottky diode JO, causing VCO to rise a VfSBD above VT, or approximately a -1.0 volt uplevel.

When either T1, or T2 or T3, or any combination of input transistors turn on and conducts ICS, the reference transistor TR turns off. This causes the opposite condition from the previous paragraph, and transistor TEO turns on causing VCO to fall to -1.5 volts and ICPNP to flow through JI causing VCI to rise to -1.0 volt.

This circuit configuration may be employed as a low-power internal circuit on an LSI type of chip. With exter al supplies of VT = -1.5 volts and VEE = -3.0 volts, the output swing from this circuit can drive another circuit capable of driving a 50...