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Shift Instruction Parity Predicts

IP.com Disclosure Number: IPCOM000084616D
Original Publication Date: 1975-Dec-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 42K

IBM

Related People

Tarolli, A: AUTHOR

Abstract

Shift instruction parity predicts are performed by checking on the bits that are actually used in the operand. This scheme predicts parity using one circuit per bit. Presently, the entire shift logic is duplicated.

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Shift Instruction Parity Predicts

Shift instruction parity predicts are performed by checking on the bits that are actually used in the operand. This scheme predicts parity using one circuit per bit. Presently, the entire shift logic is duplicated.

The controls and count fields that are generated for the shift logic do not require additional controls. The bits in the operand to be shifted are logically degated by the decode of the shift count. The result passes through a parity generator with the final parity bit being the predicted parity. The generated predicted parity bit is then compared for equality to the generated parity bit from the shift logic.

Fig. 1 shows degating the various bits with the count (CNT) field, which achieves the same result as the shifted operand except that the bits are not in their proper bit position. Also, degating only requires eight AND circuits, one per bit.

If a byte is defined as 8 bits, with bit 0 as the high-order bit (leftmost bit) and bit 7 as the low-order bit (rightmost bit), then degating the bits in the operand to be shifted is accomplished by degating bit 0 with a Shift Left Count (SLC) of 1-7; bit 1 with a SLC of 2-7; bit 2 with a SLC of 3-7; bit 3 with a SLC of 4-7; etc., to bit
6. For a byte operation, bit 7 is not degated. The following is an example of a shift left of 4: Bit position P 0 1 2 3 4 5 6 7 Operand to be shifted 0 0 1 1 1 0 1 0 1 Output of degating logic 0 0 0 0 0 1 0 1 Predicted parity 1 Result of shift operation 1 0 1 0 1 0 0 0 0 (with generated parity).

If a parallel halfword shifter is used, the logic in Fig. 1 is dupli...