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Integrated Harper Cell Disclosure Number: IPCOM000085028D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 97K

Publishing Venue


Related People

Beers, HR: AUTHOR [+5]


Described is an improved means of realizing Harper memory cells in a monolithic read/write array.

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Integrated Harper Cell

Described is an improved means of realizing Harper memory cells in a monolithic read/write array.

Referring to Figs. 1, and 3, the integrated Harper cell is a monolithic structure including three individually isolated portions: a first portion including an ion- implanted emitter resistor Re, and second and third portions each containing a double-emitter transistor TX1, TX2, an ion-implanted load resistor R1, R2 and a Schottky barrier diode D1, D2.

The integrated Harper cell of Fig. 1 offers several significant advantages over the conventional Harper cell of Fig. 2. These advantages are: 1. Area - Integration of the ion-implanted load resistor with the transistor base eliminates one contact and the metallurgy to connect it to the base. The integration is performed by extending the ion implant into the base region. Further advantage is gained by the unique placement of one emitter between the integrated base-resistor intersection and the extrinsic base contact. This introduces an additional component of load resistance, shown schematically as R3, R4, thereby reducing the total area required to realize a given load resistor value. 2. Performance - Performance of the integrated

Harper cell and a memory array incorporating the cell is improved, due to reduced subcollector to isolation - substrate capacitance (due to the area reduction) and due to the capacitive coupling from the load resistor component R3, R4 to the collector. This coupling, sho...