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# Serial Binary Multiplier

IP.com Disclosure Number: IPCOM000085046D
Original Publication Date: 1976-Feb-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 2 page(s) / 70K

IBM

## Related People

Beraud, JP: AUTHOR

## Abstract

This is a series multiplier for binary numbers (10 bits each) using very simple logic networks suitable for large-scale integration (LSI).

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Serial Binary Multiplier

This is a series multiplier for binary numbers (10 bits each) using very simple logic networks suitable for large-scale integration (LSI).

The multiplication performed is based on the so-called uniform shifts of two method. According to this method, the multiplier is divided into two-bit groups, an extra zero being added to the high-order end, if necessary, to produce an even number of bits. Only one addition or subtraction is made for each group, and using the position of the low-order bit in the group as a reference, this addition will consist of either one time or two times the multiplicand.

The operation to be performed for any pair of bits of the multiplier is determined by examining that pair of bits plus the low-order bit of the next order pair. This may be summarized on the following table, where Yi, Yi+1 and Yi-1 are the bits tested: Yi+1 Yi Yi-1 Operation

0 0 0 No operation to be performed.

0 0 1 Add the multiplicand.

0 1 0 Add the multiplicand.

0 1 1 Add two times the multiplicand.

1 0 0 Subtract two times the multiplicand.

1 0 1 Subtract the multiplicand.

1 1 0 Subtract the multiplicand.

1 1 1 No operation to be performed.

The device for applying these principles of operation and represented in the figure, comprises two 10-bit position shift registers SR1 and SR2 provided for receiving, respectively, the multiplicand X and the multiplier Y terms in series by bit, one buffer register BUF, a composer COMP and three adders Sigma A, Sigma B and Sigma C.

Shift register SR1 will provide to the composer the terms X, 2/1/X, 2/2/ X,..., 2/9/X in series. The mult...