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Digital Filter Having Integral Coefficients Disclosure Number: IPCOM000085263D
Original Publication Date: 1976-Mar-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 41K

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Tubiana, M: AUTHOR


A digital filter computes each sample Y of the filtered output signal by. performing: (Image Omitted)

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Digital Filter Having Integral Coefficients

A digital filter computes each sample Y of the filtered output signal by. performing:

(Image Omitted)

Shown in the figure is a digital filter having integral coefficients which does not require the use of any binary multiplier. The figure illustrates such a filter, assuming the number of coefficients is limited to three and the value of each coefficient is expressed in the form of a 4-bit word.

Input samples X(i-n) are applied to the input of a compression circuit comprising shift register SR1, two AND gates 1 and 2, an 0R gate, inverter I, and inhibit gate G1 controlled by the READ signal. Gate G1 prevents input samples in SRl from being read twice in one input sample period 1/Fs. Shift register SR1 runs at Fc=4Fs.

Coefficients A(1), A(2), A(3) are stored in shift register SR2 and circulate at Fc. The contents of the first stage of SR1 is gated into shift register SR3 through inhibit gate G1 and AND gates G2-G5. Gates G2-G5 are controlled by the four bits of the coefficient in the first stage of SR2, G2 being controlled by the least significant bit (LSB) and G5 by the most significant bit (MSB) of the coefficient.

The contents of SR3 is accumulated in an add and shift accumulator illustrated by adder ADD and register Rg. Gate G6 provides the output samples at times defined by the READ signal.

In the example shown on the figure:

Y(i) = A(1)X(i-1) + A(2)X(i-2) + A(3)X(i-3).

Assuming the contents of SR3 and register Rg have been reset to zero, A(3) and X(i-3) are available in the first stage of SR2 and SR1, respectively. Gate G1 is conductive and gates G2-G5 are selectively rendered conductive according to the value of A . Assuming, for example, A(3) = 0011, only gates G2 and G3 are rendered conductive and X(i-3) is loaded into the first and second stages of SR3.

The product A(3)X(i-3) is obtained through a sequence of shif...