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Highly Designable Josephson Binary Nonlatching Logic Circuits

IP.com Disclosure Number: IPCOM000085747D
Original Publication Date: 1976-May-01
Included in the Prior Art Database: 2005-Mar-02
Document File: 3 page(s) / 51K

IBM

Related People

Schlig, ES: AUTHOR

Abstract

Complementary (push-pull) Josephson binary, nonlatching, logic circuits are known in the prior art. These circuits require junctions of different sizes, bias control currents, or both to operate in a binary mode. Recent analysis reveals that tolerances must be very tight. In the known prior art, gates and/or controls are interconnected in complex ways to achieve the required phasing, resulting in space consuming circuit layouts. Also each input connects to a control of all junctions in the circuit, and each junction has several controls.

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Highly Designable Josephson Binary Nonlatching Logic Circuits

Complementary (push-pull) Josephson binary, nonlatching, logic circuits are known in the prior art. These circuits require junctions of different sizes, bias control currents, or both to operate in a binary mode. Recent analysis reveals that tolerances must be very tight. In the known prior art, gates and/or controls are interconnected in complex ways to achieve the required phasing, resulting in space consuming circuit layouts. Also each input connects to a control of all junctions in the circuit, and each junction has several controls.

Described is a binary, nonlatching, complementary circuit with junctions of equal size, no bias control currents, no interconnections between controls or special phasing, and consequently a circuit having improved tolerances. Each junction has only one control.

In the discussion below, the power supply is designated simply as a constant voltage V. Referring to Figs. 1-4, V(1) - V(2) = V. V(1) or V(2) may, if desired, be ground. V is somewhat smaller than the junction gap voltage.

The circuit of Fig. 1 shows a two-input NAND gate and differs from known circuits in that input A controls only gate Alpha and input B controls only gate Beta, and each junction has only one control. Both junctions have symmetrical I(g) vs. I(c) (gain) curves so that control currents of either polarity are equally effective.

Ignoring the polarity of the inputs, the circuit of Fig. 1 has four states corresponding to the four logical input combinations as follows:

(Image Omitted)

The logical function is NAND. (By changing the definition of logical 1 and 0, the function would be NOR.)

In the 00 state, which junction switches depends upon the previous state, the sequence of input changes and noise or stray imbalances. In the 11 state, AC current is generated which appears in the output unless it is filtered out. The frequency is high enough (484 CHz/mV) so that the AC may not influence the logical operation significantly.

Filtering, if needed, may be achieved by a series inductance, shunt capacitance, series or parallel delay line stubs, periodic line segments or Josephson junction wave traps as known in the art. One particularly advantageous stub scheme will be described. In the other states, A...