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Memory Word Line Monitor Disclosure Number: IPCOM000086046D
Original Publication Date: 1976-Jul-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 28K

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This is a technique for detecting a failure in memory operation.

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Memory Word Line Monitor

This is a technique for detecting a failure in memory operation.

During write, memory word line failures go undetected until read-back. They can go completely undetected in both read and write particularly with: simple parity checking, multiple bits per word line (often a whole byte and its parity), and unpredictable sense amplifier outputs.

The presently described technique monitors the word lines with detectors whose outputs are gated together by the OR circuit shown in the drawing.

The proper activation of any word line results in a signal at the output of the OR gate. This signal is interrogated during writing and reading. The absence of a signal signifies an error.


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